SKU/Artículo: AMZ-3319139053

A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof (Theoretical Computer Science and General Issues)

Format:

Paperback

Kindle

Paperback

Detalles del producto
Disponibilidad:
En stock
Peso con empaque:
0.69 kg
Devolución:
No
Condición
Nuevo
Producto de:
Amazon
Viaja desde
USA

Sobre este producto
  • This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.
U$S 136,30
60% OFF
U$S 54,52

IMPORTÁ FACIL

Comprando este producto podrás descontar el IVA con tu número de RUT

NO CONSUME FRANQUICIA

Si tu carrito tiene solo libros o CD’s, no consume franquicia y podés comprar hasta U$S 1000 al año.

U$S 136,30
60% OFF
U$S 54,52

¡Comprá en hasta 12 cuotas sin interés con todas tus tarjetas!

Llega en 15 a 25 días hábiles
con envío
Tienes garantía de entrega